1. Field of the Invention
The present invention relates to an integrated circuit layout, especially to a capacitor layout of an integrated circuit.
2. Description of Related Art
Regarding a successive approximation register analog-to-digital conversion integrated circuit (SAR ADC IC), a digital-to-analog converter (DAC) plays an important role. A known type of the DAC is a capacitive DAC (CDAC). A CDAC uses a plurality of capacitor groups of different sizes (e.g., 256C, 128C, . . . , 4C, 2C, 1C, 1C, in which “C” is a designed unit of capacitance) through the control over switches to successively output a plurality of analog signals gradually approaching an input signal, and thus an SAR ADC IC can successively compare a sampled value of the input signal with the analog signals outputted by the CDAC to obtain digital bits of the input signal. The plurality of capacitor groups should match, which means that the ratio of the capacitance of one capacitor group to the capacitance of another capacitor group should be accurate/reliable, so as to allow the analog signals of the CDAC to be generated accurately for gradually approaching the input signal and make sure that each digital bit of the input signal is correct.
In light of the above, when manufacturing an IC (especially with an advanced process), the matching property of capacitor groups of a CDAC is dependent upon whether the layout (or circuit density) of the capacitor groups and their neighboring elements is uniform. Generally, the better the uniformity of the layout, the better the matching property. Therefore, As shown in FIG. 1 illustrating a conventional capacitor layout 100 of a CDAC, the capacitor groups are surrounded by dummy capacitors which ensures that the circuitry density of the edge of the layout of the capacitor groups (hereafter, the capacitor group layout) is similar to the circuitry density of the inside of the capacitor group layout, so as to make sure the matching property of actually manufactured capacitor groups would be reliable. In FIG. 1, different capacitor groups (i.e., capacitor group 4C, capacitor group 2C, and capacitor group 1C) are labeled with different numbers (4, 2, and 1) respectively, while the dummy capacitors are labeled with “D”. In FIG. 1, the electrode circuits 110, 120 of each capacitor unit in the capacitor groups shouldn't be short-circuited so as to generate capacitance; meanwhile, the electrode circuits 130, 140 of each dummy capacitor should be short-circuited so as to prevent generating capacitance. However, as shown in FIG. 2, parasitic capacitance (as indicated by the dotted lines in FIG. 2) is generated between any two capacitor units in the capacitor groups while no substantial parasitic capacitance is generated between any capacitor unit at the edge of the capacitor group layout and any dummy capacitor. As a result, the effective capacitance of a capacitor unit at the edge of the capacitor group layout is substantially different from the effective capacitance of a capacitor unit at the inside of the capacitor group layout, and this difference will affect the correctness of digital-to-analog conversion. For example, the capacitance proportions of the capacitor groups (i.e., capacitor group 4C, capacitor group 2C, and capacitor group 1C) in FIG. 1 are supposed to be 4:2:1, but they are 18.66695:9.338976:4.670652 in reality due to the influence of the said parasitic capacitances. This deviation of the capacitance proportions leads to a bad linearity of the CDAC, and makes the CDAC unfavorable to a high definition application.
People who are interested in the prior art may refer to the following literature: Chun-Cheng Liu, et al., “A 1V 11fJ/Conversion-Step 10 bit 10 MS/s Asynchronous SAR ADC in 0.18 μm CMOS”, 2010 Symposium on VLSI Circuits/Technical Digest of Technical Papers.